IND165SK View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
IND165SK Datasheet PDF : 41 Pages
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Data Sheet
Figure 2.1 shows how to perform the configuration with external logic.
SB0
0
1
2
EN2 EN1
BUF
4
4
cfg0
EN2 EN1
BUF
4
4
cfg1
EN2
EN1
BUF
4
4
cfg2
CFG_CYC
CFG_SEL[3:0]
(SB0_D[3:0])
INDT
CFG_CYC
CFG_SEL[3:0]
(SB2_D[3:0])
INDR
0
1
SB2 2
3
CFG_D[3:0]
(SB2_D[3:0])
CFG_D[3:0]
(SB0_D[3:0])
INDT/R165B
INDT/R330B
0
1
2
SB2
3
cfg0
EN1 EN2
BUF
4
4
cfg1
EN1 EN2
BUF
4
4
EN1 EN2
cfg2
BUF
4
4
EN1
EN2
cfg3
BUF
4
4
0
1
2
3
SB0
Figure 2.1: Configuration Logic
Each configuration vector’s default setting is “1111”. This popular operating mode (see light gray lines on following tables)
can easily be established with pull-up resistors from the configuration inputs to VCC instead of tri-state buffers. All
configuration vectors are valid for transmitter and receiver, unless otherwise noted.
2.2 Configuration Process and Timing
Figure 2.2 shows the configuration process.
RESET#
CF G _C YC
CFG_SEL[3:0] 0x0
0x1 0x0 0x2 0x0 0x4 0x0 0x8 0x0
CFG_D[3:0]
Internal clock
registers
config data
cfg0
cfg1
cfg2
cfg3
Date: 2005-02-18 Revision: 1.1
Figure 2.2: Timing of Configuration Process
Page 13 of 41
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