IL8583D View Datasheet(PDF) - IK Semicon Co., Ltd

Part Name

Description

Manufacturer

IL8583D

CMOS timer with RAM and I2C-bus control

IK Semicon Co., Ltd 

INA8583

The year and date are packed into memory location 05. The weekdays and months

are packed into memory location 06. When reading these memory locations the year and

weekdays may be masked out when the mask flag of the control/status register is set.

This allows the user to read the date and month counters only.

In the event counter mode data are stored in BCD format. D5 is the most significant

and do the least significant digit. In this mode the internal divider is by-passed.

By setting the alarm enable bit of the control/status register the alarm control register (ad-

dress 08) is activated. All functions of the alarm, timer and interrupt output are controlled

by the contents of the alarm control register.

All alarm registers are arranged starting from 08 address.

An alarm signal is generated when the contents of the alarm registers matches bit-

by-bit the contents of the involved counter registers. The year and weekday bits are ig-

nored in a dated alarm. A daily alarm ignored the month and date bits. When a weekday

alarm is selected, for comparison a bit will be selected from the alarm register per the

weekday (address OE) corresponding to the weekday on which the alarm is activated.

Interrupt output (with open drain) is programmed by setting the alarm control regis-

ter. It enables (active LOW) when the alarm flag or timer flag are set. The voltage level in

ON state (HIGH) on the interrupt output may be more than the supply voltage.

A 32.768 kHz quartz crystal may be connected to OSCI (pin 1) and OSCO (pin 2).

A trimmer capacitor between OSCI and supply is used for tuning the oscillator. A 100 Hz

clock signal is derived from the quartz oscillator for the clock counters.

In the 50Hz clock mode or event-counter mode the oscillator is disabled and the

oscillator input is switched to a high impedance state. This allows the user to feed the

50Hz reference frequency or an external high speed event signal into the input OSCI.

When power-up occurs the I2C-bus interface, the control/status register and all

clock counters are reset. After the device starts time-keeping in the 32.768kHz clock mode

with the 24hr format on the square wave appears at the interrupt output pin (starts HIGH).

This may be abolished by setting the alarm enable bit in the control/status register.

The 2nd signal of interface of I2C-bus is generated as soon as the supply voltage

below the reset level of I2C-bus interface. This reset signal does not affect the registers of

hour counter and control/status register.

It the recommended to set the stop counting flag of the control/status register be-

fore loading the actual time into the counters. Loading of illegal states may lead to a tem-

porary clock malfunction.

I2C-bus is a bi-directional, two-line communication between different ICs and mod-

ules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines

shall be connected to a positive supply via a resistor since in IC these outputs have “open

drain”. Data transfer may be initiated only when the bus is not busy.

2012, January, ver.01

Share Link: