IT8673F View Datasheet(PDF) - ITE Tech. INC.

Part Name

Description

Manufacturer

IT8673F

Advanced Input / Output (Advanced I/O)

ITE Tech. INC. 

Table 11-3. Digital Output Register (DOR)........................................................................................................ 49

Table 11-4. Tape Drive Register (TDR) ............................................................................................................ 49

Table 11-5. Main Status Register (MSR) .......................................................................................................... 50

Table 11-6. Data Rate Select Register (DSR)................................................................................................... 51

Table 11-7. Data Register (FIFO)...................................................................................................................... 51

Table 11-8. Digital Input Register (DIR) ............................................................................................................ 52

Table 11-9. Diskette Control Register (DCR) .................................................................................................... 52

Table 11-10. Status Register 0 (ST0)................................................................................................................ 53

Table 11-11. Status Register 1 (ST1)................................................................................................................ 54

Table 11-12. Status Register 2 (ST2)................................................................................................................ 55

Table 11-13. Status Register 3 (ST3)................................................................................................................ 55

Table 11-14. Command Set Symbol Descriptions ............................................................................................ 56

Table 11-15. Command Set Summary.............................................................................................................. 58

Table 11-16. Effects of MT and N Bits .............................................................................................................. 66

Table 11-17. SCAN Command Result .............................................................................................................. 68

Table 11-18. VERIFY Command Result ........................................................................................................... 69

Table 11-19. Interrupt Identification................................................................................................................... 71

Table 11-20. HUT Values .................................................................................................................................. 71

Table 11-21. SRT Values .................................................................................................................................. 72

Table 11-22. HLT Values................................................................................................................................... 72

Table 11-23. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands........................ 72

Table 11-24. Effects of Drive Mode and Data Rate on FORMAT A TRACK and WRITE DATA Commands... 73

Table 11-25. Serial Channel Registers ............................................................................................................. 74

Table 11-26. Interrupt Enable Register Description .......................................................................................... 75

Table 11-27. Interrupt Identification Register .................................................................................................... 76

Table 11-28. FIFO Control Register Description ............................................................................................... 77

Table 11-29. Receiver FIFO Trigger Level Encoding........................................................................................ 77

Table 11-30. Baud Rates Using (24 MHz ÷ 13) Clock....................................................................................... 78

Table 11-31. Line Control Register Description ................................................................................................ 79

Table 11-32. Stop Bits Number Encoding ......................................................................................................... 79

Table 11-33. Modem Control Register Description ........................................................................................... 80

Table 11-34. Line Status Register Description.................................................................................................. 81

Table 11-35. Modem Status Register Descriptiopn........................................................................................... 82

Table 11-36. Reset Control of Registers and Pinout Signals............................................................................ 83

Table 11-37. Parallel Port Connector in Different Modes.................................................................................. 85

Table 11-38. Address Map and Bit Map for SPP and EPP Modes ................................................................... 86

Table 11-39. Bit Map of the ECP Registers ...................................................................................................... 89

Table 11-40. ECP Register Definitions.............................................................................................................. 89

Table 11-41. ECP Mode Descriptions ............................................................................................................... 89

Table 11-42. ECP Pin Descriptions ................................................................................................................... 90

Table 11-43. Extended Control Register (ECR) Mode and Description............................................................ 92

Table 11-44. Data Register READ/WRITE Controls ......................................................................................... 96

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