LA73024AV View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LA73024AV Datasheet PDF : 12 Pages
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LA73024AV
Serial Control Specification
Slave address
MSB
LSB
1
0
0
1
0
0
0
0
↑
Slave receiver
Data format
S
Slave address (8bit)
A Sub address (8bit) A
↑
↑
Start condition
Acknowledge
Data address (8bit) A P
↑
Stop condition
Sub address and data byte table
Sub address
Hexadecimal
01
(0000 0001)
D8
D7
SW1
00: C
01: B
10: A
11: A
Data byte (Underline is initial setting.)
D6
D5
D4
D3
SW2
00: D
01: C
10: B
11: A
SW3
00: C
01: B
10: A
11: *
02
(0000 0010)
03
(0000 0011)
EXT
CTL1
0: L
1: H
MUTE1
VSW1 OUT
0: through
1: MUTE
EXT
CTL2
0: L
1: H
MUTE2
VSW2 OUT
0: through
1: MUTE
AMP GAIN
VPS OUT
0: 0dB
1: 6dB
MUTE3
VSW3 OUT
0: through
1: MUTE
AUDIO AMP GAIN1
(DEC OUT)
000: 0dB
001: 2dB
010: 4dB
011: 6dB
100:12dB
MUTE4
MUTE5
MUTE6
ASW1 OUT ASW2 OUT ASW3 OUT
0: through
1: MUTE
0: through
1: MUTE
0: through
1: MUTE
D2
D1
FSSOUT
00: HIGH
01: HIGH
10: MID
11: LOW
AUDIO AMP GAIN2
(EXT OUT)
00: 0dB
01: 2dB
10: 4dB
11: 6dB
EXT
CTL3
EXT
CTL4
0: L
0: L
1: H
1: H
Data transfer
I2C-BUS control system is adopted in SW IC and SW IC is controlled by SCL (Serial Clock) and SDA (Serial Data) At
first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data
which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data
transfer order (MSB → LSB). The 9th bit is called as ACK (Acknowledge), SW IC sends [0] to the SDA terminal
during SCL [1] period. So, please open the port of micro-processor during this period. LA73024AV adopt
auto-increment, so you input only first sub-address data (called as Group) and you can transfer data in order. As thus
the Data transfer Stop condition*2 is finished.
*1 SDA rise up during SCI is [1]
*2 SDA fall down during SCL is [1]
No.A0238-9/12
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