MAC7100 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MAC7100

MAC7100 Microcontroller Family Hardware Specifications

Motorola => Freescale 

Freescale Semiconductor, Inc.

Electrical Characteristics

3.10 Analog-to-Digital Converter Characteristics

Table 24 and Table 25 show conditions under which the ATD operates. The following constraints exist to

obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists because the

sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside

of this range it will effectively be clipped.

Table 24. ATD Operating Characteristics in 5 V Range

Conditions shown in Table 6 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

M1 D Reference Potential

M2 C Differential Reference Voltage 1

Low VRL

High VRH

VRH – VRL

VSSA

VDDA ÷ 2

4.50

—

—

5.00

VDDA ÷ 2 V

VDDA

V

5.25

V

M3 D ATD Clock Frequency

fATDCLK

0.5

—

2.0

MHz

M4 D ATD 10-bit Conversion PeriodClock Cycles 2

NCONV10

14

—

28 Cycles

@ 2.0MHz fATDCLK TCONV10

7

—

14

µs

M5 D ATD 8-bit Conversion PeriodClock Cycles 2

NCONV8

12

—

26 Cycles

@ 2.0MHz fATDCLK TCONV8

6

—

13

µs

M6 D Recovery Time (VDDA = 5.0 V)

tREC

—

—

20

µs

M7 P Reference Supply current 1 ATD module enabled IREF

—

—

0.375

mA

M8 P Reference Supply current 2 ATD modules enabled IREF

—

—

0.750

mA

1 Full accuracy is not guaranteed when differential voltage is less than 4.50 V

2 Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.

Table 25. ATD Operating Characteristics in 3.3 V Range

Conditions shown in Table 6, with VDDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted.

Num C

Rating

Symbol

Min

Typ

Max

Unit

N1 D Reference Potential

N2 C Differential Reference Voltage 1

Low VRL

VSSA

—

VDDA ÷ 2 V

High VRH

VDDA ÷ 2

—

VDDA

V

VRH–VRL

3.0

3.3

3.6

V

N3 D ATD Clock Frequency

fATDCLK

0.5

—

2.0

MHz

N4 D ATD 10-bit Conversion PeriodClock Cycles 2

NCONV10

14

—

28 Cycles

Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10

7

—

14

µs

N5 D ATD 8-bit Conversion PeriodClock Cycles 2

NCONV8

12

—

26 Cycles

Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV8

6

—

13

µs

N6 D Recovery Time (VDDA=5.0 V)

tREC

—

—

20

µs

N7 P Reference Supply current 1 ATD module enabled IREF

—

—

0.375

mA

N8 P Reference Supply current 2 ATD modules enabled IREF

—

—

0.250

mA

1 Full accuracy is not guaranteed when differential voltage is less than 3.0 V

2 Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.

3.10.1 Factors Influencing Accuracy

Three factors — source resistance, source capacitance and current injection — have an influence on the

accuracy of the ATD.

23

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

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