MAX5940AESA View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX5940AESA Datasheet PDF : 15 Pages
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IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Table 1. PD Power Classification/RCL Selection
CLASS
0
USAGE
Default
1
Optional
2
Optional
3
Optional
4
Not Allowed
*Class 4 reserved for future use.
RCL (Ω)
10k
732
392
255
178
MAXIMUM POWER USED BY PD (W)
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
Reserved*
Table 2. Setting Classification Current
CLASS
0
1
2
3
4
RCL (Ω)
10k
732
392
255
178
VIN* (V)
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
CLASS CURRENT SEEN AT VIN (mA)
MIN
0
9.17
17.29
26.45
36.6
MAX
2
11.83
19.71
29.55
41.4
IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
MIN
MAX
0
4
9
12
17
20
26
30
36
44
*VIN is measured across the MAX5940 input pins, which does not include the diode bridge voltage drop.
Classification Mode (12.6V ≤ VIN ≤ 20V)
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distri-
bution. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor (RCL)
connected from RCLASS to VEE sets the classification
current.
The PSE determines the class of a PD by applying a volt-
age at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5940_ exhibit a current charac-
teristic with values indicated in Table 2. The PSE uses the
classification current information to classify the power
requirement of the PD. The classification current includes
the current drawn by the 25.5kΩ detection signature
resistor and the supply current of the MAX5940_ so the
total current drawn by the PD is within the IEEE 802.3af
standard figures. The classification current is turned off
whenever the device is in power mode.
Power Mode
During power mode, when VIN rises above the under-
voltage lockout threshold (VUVLO,ON), the MAX5940_
gradually turn on the internal N-channel MOSFET Q1
(see Figure 2). The MAX5940_ charge the gate of Q1
with a constant current source (10µA, typ). The drain-
to-gate capacitance of Q1 limits the voltage rise rate at
the drain of the MOSFET, thereby limiting the inrush
current. To reduce the inrush current, add external
drain-to-gate capacitance (see the Inrush Current Limit
section). When the drain of Q1 is within 1.2V of its
source voltage and its gate-to-source voltage is above
5V, the MAX5940_ asserts the PGOOD/PGOOD out-
puts. The MAX5940_ have a wide UVLO hysteresis and
turn-off deglitch time to compensate for the high
impedance of the twisted-pair cable.
Undervoltage Lockout
The MAX5940_ operate up to a 67V supply voltage with a
default UVLO turn-on (VUVLO,ON) set at 35V
(MAX5940A/MAX5940C) or 39V (MAX5940B/MAX5940D)
and a UVLO turn-off (VUVLO,OFF) set at 30V. The
MAX5940B/MAX5940D have an adjustable UVLO thresh-
old using a resistor-divider connected to UVLO (see
Figure 3). When the input voltage is above the UVLO
threshold, the IC is in power mode and the MOSFET is
on. When the input voltage goes below the UVLO thresh-
old for more than tOFF_DLY, the MOSFET turns off.
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