MT16LSDT6464A View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT16LSDT6464A

SYNCHRONOUS DRAM MODULE

Micron Technology 

256MB / 512MB (x64)

168-PIN SDRAM DIMMs

SPD EEPROM TIMING DIAGRAM

tF

tHIGH

tR

tLOW

SCL

tSU:STA

tHD:STA

tHD:DAT

tSU:DAT

tSU:STO

SDA IN

SDA OUT

tAA

tDH

tBUF

UNDEFINED

Table 21: Serial Presence-Detect EEPROM AC Operating Conditions

VDD = +3.3V ±0.3V; All voltages referenced to VSS

PARAMETER/CONDITION

SCL LOW to SDA data-out valid

Time the bus must be free before a new transition can

start

Data-out hold time

SDA and SCL fall time

Data-in hold time

Start condition hold time

ClockHIGHperiod

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

SDA and SCL rise time

SCL clock frequency

Data-in setup time

Start condition setup time

Stop condition setup time

WRITE cycle time

SYMBOL

tAA

tBUF

tDH

tF

tHD:DAT

tHD:STA

tHIGH

tI

tLOW

tR

fSCL

tSU:DAT

tSU:STA

tSU:STO

tWRC

MIN

0.3

4.7

300

0

4

4

4.7

250

4.7

4.7

MAX

3.5

–

300

100

1

100

10

UNITS

µs

µs

ns

ns

µs

µs

µs

ns

µs

µs

KHz

ns

µs

µs

ms

NOTES

1

NOTE:

1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA

remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

32,64 Meg x 64 SDRAM DIMMs

SD8_16C32_64x64AG_C.fm - Rev. C 11/02

20

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology Inc.

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