DC and AC parameters
Figure 30. Resistor value versus waveform timings for Ready/Busy signal
NAND512-A2C
400
300
200
1.7
100
30
0 1.7
1
1. T = 25°C.
VDD = 1.8V, CL = 30pF
VDD = 3.3V, CL = 100pF
4
400
3
2
0.85
90
60
0.57
1.7
1.7
2
3
RP (KΩ)
120
1
0.43
1.7
4
tf
300
2.4
200
300
200
1.2
100 100
0.8
0 3.6
1
3.6
3.6
2
3
RP (KΩ)
tr
ibusy
4
400
3
2
1
0.6
3.6
4
ai07565B
10.2
Data Protection
The Numonyx NAND device is designed to guarantee Data Protection during Power
Transitions.
A VDD detection circuit disables all NAND operations, if VDD is below the VLKO threshold.
In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept
low (VIL) to guarantee hardware protection during power transitions as shown in the below
figure.
Figure 31. Data Protection
VDD
Nominal Range
VLKO
Locked
WP
Locked
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