S5L9290X01-L0R0 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

S5L9290X01-L0R0

DIGITAL SIGNAL PROCESSOR FOR CDP

Samsung 

PRELIMINARY

S5L9290X

DIGITAL SIGNAL PROCESSOR FOR CDP

$8D Command

Digital PLL control

Command Address

DPLL control 5

10001101

($8D)

D7

CMD

SPLIT

D6

PHASE

ONLY

Data

D5

D4

D3

D2

D1

D0

MRANGE[1:0]

FSREG

PLLTEST

PLL

PWRDN1

-

CMD_SPLIT (option)

The digital PLL control micom command is automatically applied when the speed is changed($F0) or

at Jitter Free2($94).

H : Each DPLL control Micom Commands ($8A, $8B, $8B) are applied using the Micom Interface terminals

(MCK, MDAT, MLT).

L : DPLL control Micom Command ($8A, $8B, $8B) is applied automatically inside.

PHASE_ONLY (option)

Controls phase compensation status at DPLL.

H : Phase compensation

L : Phase compensation + Frequency compensation

MRANGE[1:0]

Controls the range of the PLL1 Main Divider M value range

Bits

D[5:4]

Name

MRANGE[1:0]

Data = 00

50%

Data = 01

40%

Data = 10

30%

FSREG

Verifies the Frame Sync status(|Thigh-Tlow| ≤ 1) at MAX T

H : Verify

L : Ignore

PLLTEST

PLL1 TEST mode

H : TEST (M1<=M2),

L : Normal

PLL PWDN1

PLL1 Power Down mode

H : Power Down,

L : Normal

Data = 11

20%

Comment

Lock Range

14

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