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SPH4692 View Datasheet(PDF) - Siemens AG

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SPH4692 Datasheet PDF : 22 Pages
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SPH 4692
Pin 18
The zero detector controlling the logic block recognizes the transformer being discharged by
positive to negative zero crossing of pin 18 voltage and enables the logic for a new pulse. Parasitic
oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an
internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per page 133 is represented on page 135 for a line
voltage barely above the lower acceptable limit time t0 the following voltages built up:
V16 corresponding to the half-wave charge current over R1
V2 to V2 max (typically 6.6 V)
V3 to the value determined by the divider R10/R11.
The current drawn by the IC in this case is less than 0.8 mA.
If V16 reaches the threshold V16 E (time point t1), the IC switches on the internal reference voltage.
The current draw max. rises to 12 mA. The primary current-voltage reproducer regulates V2 down
to V2B and the starting impulse generator generates the starting impulses from time point t5 to t6.
The feedback to pin 18 starts the next impulse and so on. All impulses including the starting impulse
are controlled in width by regulating voltage of pin 1. When switching on this corresponds to a short-
circuit event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width
depending on the regulating voltage feedback (the IC operates in the overload range). The IC
operates at the overload point. Thereafter the peak values of V2 decrease rapidly, as the starting
attempt is aborted (pin 15 is switched to low). As the IC remains switched on, V16 further decreases
to V16. The IC switches off; V16 can rise again (time point t4) and a new start-up attempt begins at
time point t1. If the rectified alternating line voltage (primary voltage) collapses during load, V3 can
fall below V3 A , as is happening at time point t3 (switch-on attempt when voltage is too low). The
primary voltage monitor then clamps V3 to V3 S until the IC switches off (V16 < V16 A). Then a new
start-up attempt begins at time point t1.
Semiconductor Group
7

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