STM8S103xx, STM8S105xx
Pinouts and pin description
Table 6.
Pin
number
Pin description for STM8S103 MCUs (continued)
Input
Output
Pin name
Alternate
function
Default alternate after
function
remap
[option
bit]
PC4/AIN2/TIM1_CC4/
21 13
CLK_CCO
I/O X
X
X
HS O3
X
X
Analog input 2 /
Port C4 Timer 1 - channel
4
Con-
figurable
clock
output
22 14 PC5/TIM2_CC1/SPI_SCK
I/O X
X
X
HS O3
X
X
Port C5
Timer 2 - channel
1
SPI clock
23 15 PC6/SPI_MOSI
I/O X
X
X
HS O3
X
X
Port C6
SPI master out/
slave in
24 16 PC7/SPI_MISO
I/O X
X
X
HS O3
X
X
Port C7
SPI master in/
slave out
Con-
25
- PD0/TIM1_BKIN/CLK_CCO I/O X
X
X
HS O3
X
X
Port D0
Timer 1 - break
input
figurable
clock
output
26 17 PD1/SWIM
I/O X
X
X
HS O4
X
X
Port D1
SWIM data
interface
27 18 PD2/AIN3/TIM2_CC3
Analog input 3 /
I/O X X X HS O3 X X Port D2 Timer 2 - channel
3
28
19
PD3/AIN4/TIM2_CC2/ADC_
ETR
I/O
X
X
Analog input 4 / ADC
X HS O3 X X Port D3 Timer 2 - channel external
2
trigger
29
20
PD4/TIM2_CC1/BEEP/
USART_CK
USART
I/O X
X
X
HS O3
X
X
Port D4
Timer 2 - channel
1
clock/
BEEP
output
30 1 PD5/AIN5/USART_TX
I/O X X X
O1 X X Port D5 Analog input 5
USART
data
transmit
31 2 PD6/AIN6/USART_RX
I/O X X X
O1 X X Port D6 Analog input 6
USART
data
receive
32 - PD7/TLI/TIM1_CC4
Top level interrupt/
I/O X X X HS O3 X X Port D7 Timer 1 - channel
4
1. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented)
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