LT3669EUFDPBF View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LT3669EUFDPBF

IO-Link Transceiver with Integrated Step-Down Regulator and LDO

Linear Technology 

LT3669/LT3669-2

PIN FUNCTIONS

LDOIN (Pin 18): LDO Power Supply Input. This is the

collector of the LDO power NPN. Tie to the output of the

switching regulator for maximum efficiency, or to DIO. To

preserve reverse-polarity protection, do not connect to L+.

LDO (Pin 19): Low Dropout Linear Regulator Output.

Bypass to GND with at least 1µF of capacitance.

FBLDO (Pin 20): The LT3669 regulates this pin to 0.794V.

Connect a feedback resistor divider tap to this pin to set

the output voltage of the LDO.

FBOUT (Pin 21): The LT3669 regulates this pin to 0.794V.

Connect a feedback resistor divider tap to this pin to set

the output voltage of the switching regulator.

RT (Pin 22): Sets the Internal Oscillator Frequency. Tie a

resistor from RT to AGND to program the frequency. See

Table 2 for resistor values.

AGND (Pin 23): Analog Ground Used for Bandgap Voltage

References. Connect to the ground node of the passive

components connected to RT, FBOUT, FBLDO, ILIM and

CPOR, and to the system ground in a star connection

manner.

SYNC (Pin 24): External Clock Synchronization Input.

Ground this pin to run the part using the internal oscil-

lator. For external synchronization, drive the SYNC pin

with a logic-level signal with positive and negative pulse

widths of at least 80ns. Choose the RT resistor to set the

LT3669 switching frequency at least 20% below the lowest

synchronization input. For example, if the synchronization

signal is 350kHz, the RT pin should be set for 280kHz.

SR (Pin 25): Slew Rate Control Pin. Setting SR low ad-

justs both CQ1 and Q2 drivers’ rising and falling times for

reduced EMI in COM1/COM2 speed mode. Set SR high

for edge times suitable for COM3.

ILIM (Pin 26): Line Driver Current Limit Programming

Pin. Source and sink current limits for both line drivers

are programmed using this pin. Tie a resistor from ILIM

to AGND to set the drivers output current limit. Tie ILIM

to AGND for a 140mA current limit.

CPOR (Pin 27): Reset Delay Timer Programming Pin.

Connect an external capacitor (CPOR) to AGND to program

a reset delay time of 0.125ms/nF.

RST (Pin 28): Active Low, Open-collector Logic Output.

After VOUT and VLDO rises above 92.7% of its programmed

value, the reset remains asserted for the period set by the

capacitor on the CPOR pin. RST will also pull low if VL+

is below the internal undervoltage threshold and VOUT or

VLDO are above 1.5V for an RST pull-up resistor of 100k. If

using the POR function, connect a 10pF capacitor between

the CPOR and RST pins.

GND (Pin 29 Exposed Pad): Ground. Tie the exposed pad

directly to the ground plane and the industrial line ground

terminal. The exposed pad metal of the package provides

both electrical contact to ground and good thermal contact

to the circuit printed board. It must be soldered to the

circuit board for proper operation.

For more information www.linear.com/LT3669

3669fa

13

Share Link: