LT3669EUFD-2 View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LT3669EUFD-2

IO-Link Transceiver with Integrated Step-Down Regulator and LDO

Linear Technology 

LT3669/LT3669-2

APPLICATIONS INFORMATION

(see Figure 24). On power-down, once the output voltage

drops below RST threshold, RST is held at a logic low. The

reset timer is adjustable using an external capacitor. The

POR comparator is designed to be robust against FBOUT

and FBLDO pin noise, which could potentially false-trigger

the RST pin. The POR comparator lowpass filters the first

stage of the comparator. This filter integrates the output

of the comparator before asserting the RST. The benefit

of adding this filter is that any transients at the buck

regulator’s output must be of sufficient magnitude and

duration before it triggers a logic change in the output.

This prevents spurious resets caused by output voltage

transients, such as load steps or short brownout condi-

tions, without sacrificing the DC reset threshold accuracy.

The RST signal also resets the internal wake-up latch. A

wake-up event can then only be flagged when the RST

signal goes high.

Selecting the Reset Timing Capacitor

The reset timeout period is adjustable in order to accom-

modate a variety of microprocessor applications. Set the

reset timeout period, (tRST), by connecting a capacitor,

CPOR, between the CPOR pin and ground, with value

determined by:

CPOR

=

tRST

•

8000

pF

ms

This equation is accurate for reset timeout periods of

1.0ms, or greater. To program faster timeout periods,

see the Reset Timeout Period vs Capacitance graph in

the Typical Performance Characteristics section. Leaving

the CPOR pin unconnected will generate a minimum reset

timeout of approximately 22μs. Maximum reset timeout

is limited by the largest available low leakage capacitor.

The accuracy of the timeout period will be affected by

capacitor leakage (the nominal charging current is 10μA)

and capacitor tolerance. A low leakage ceramic capacitor

is recommended.

To prevent noise from false tripping the comparator on

the CPOR pin, place a 10pF capacitor between the RST

and CPOR pins. The rising edge of RST coupled into the

CPOR pin ensures generating a clean reset signal.

IO-Link Disclaimer

Linear Technology attempts to maintain compatibility with

the IO-Link interface and system specifications. LTC is

not a member of the IO-Link Consortium as set forth by

PROFIBUS Nutzerorganisation (PNO) e.V.

VEN/UVLO

5V/DIV

VRST

5V/DIV

VOUT

2V/DIV

12.5ms

VLDO

2V/DIV

CPOR = 0.1µF

5ms/DIV

0V

0V

0V

36692 F24

Figure 24. Reset Timer Waveforms

For more information www.linear.com/LT3669

3669fa

35

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