AD7663 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7663

16-Bit, 250 kSPS CMOS ADC

Analog Devices 

AD7663

100000

10000

1000

AVDD

100

DVDD

10

1

OVDD

0.1

0.01

0.001

1

10

100

1000 10000 100000 1000000

SAMPLING RATE – SPS

TPC 13. Operating Currents vs. Sample Rate

500

450

400

350

DVDD

300

250

200

150

100

OVDD

AVDD

50

0

–55 –35 –15

5

25

45

65 85 105

TEMPERATURE – ؇C

TPC 14. Power-Down Operating Currents vs. Temperature

10

8

6

4

–FS

2

OFFSET

0

+FS

–2

–4

–6

–8

–10

–55 –35 –15 5

25 45 65 85 105 125

TEMPERATURE – ؇C

TPC 15. +FS, Offset, and –FS vs. Temperature

CIRCUIT INFORMATION

The AD7663 is a fast, low power, single-supply, precise 16-bit

analog-to-digital converter (ADC). The AD7663 is capable of

converting 250,000 samples per second (250 kSPS) and allows

power saving between conversions. When operating at 100 SPS,

for example, it consumes typically only 15 µW. This feature

makes the AD7663 ideal for battery-powered applications.

The AD7663 provides the user with an on-chip track-and-hold,

successive approximation ADC that does not exhibit any pipeline

or latency, making it ideal for multiple multiplexed channel

applications.

It is specified to operate with both bipolar and unipolar input

ranges by changing the connection of its input resistive scaler.

The AD7663 can be operated from a single 5 V supply and can be

interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead

LQFP package or a 48-lead LFCSP package that combines space

savings and flexible configurations as either serial or parallel inter-

face. The AD7663 is pin-to-pin compatible with the AD7660.

CONVERTER OPERATION

The AD7663 is a successive approximation analog-to-digital

converter based on a charge redistribution DAC. Figure 3 shows

the simplified schematic of the ADC. The input analog signal is

first scaled down and level shifted by the internal input resistive

scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V,

and 0 V to 10 V) and bipolar ranges (±2.5 V, ±5 V, and ±10 V).

The output voltage range of the resistive scaler is always 0 V to

2.5 V. The capacitive DAC consists of an array of 16 binary

weighted capacitors and an additional “LSB” capacitor. The

comparator’s negative input is connected to a “dummy” capacitor

of the same value as the capacitive DAC array.

During the acquisition phase, the common terminal of the array

tied to the comparator’s positive input is connected to AGND

via SWA. All independent switches are connected to the output

of the resistive scaler. Thus, the capacitor array is used as a

sampling capacitor and acquires the analog signal. Similarly, the

dummy capacitor acquires the analog signal on INGND input.

When the acquisition phase is complete and the CNVST input

goes or is LOW, a conversion phase is initiated. When the conver-

sion phase begins, SWA and SWB are opened first. The capacitor

array and the dummy capacitor are then disconnected from the

inputs and connected to the REFGND input. Therefore, the differ-

ential voltage between the output of the resistive scaler and INGND

captured at the end of the acquisition phase is applied to the

comparator inputs, causing the comparator to become unbalanced.

By switching each element of the capacitor array between

REFGND or REF, the comparator input varies by binary

weighted voltage steps (VREF /2, VREF /4 . . . VREF /65,536). The

control logic toggles these switches, starting with the MSB first,

in order to bring the comparator back into a balanced condition.

After the completion of this process, the control logic generates

the ADC output code and brings the BUSY output LOW.

REV. B

–11–

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