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NCN4555 View Datasheet(PDF) - ON Semiconductor

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Description
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NCN4555 Datasheet PDF : 12 Pages
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NCN4555
APPLICATION INFORMATION
CARD SUPPLY CONVERTER
The NCN4555 interface DC−DC converter is a
Low Dropout Voltage Regulator capable of suppling a
current in excess of 50 mA under 1.8 V or 3.0 V. This device
features a very low quiescent current typically lower than
25 mA (Figure 6 and 7). MOD_VCC is a select input
allowing a logic level signal to select a regulated voltage of
1.8 V (MOD_VCC = LOW) or 3.0 V (MOD_VCC = HIGH).
Additionally, the NCN4555 has a shutdown input allowing
it to turn off or turn on the regulator output. The shutdown
mode power consumption is typically in the range of a few
tens of nA (30 nA Typical). Figure 8 shows a simplified
view of the NCN4555 voltage regulator. The SIM_VCC
output is internally current limited and protected against
short circuits. The short−circuit current IVCC is constant
over the temperature and SIM_VCC. It varies with VBAT
typically in the range of 60 mA to 90 mA (Figure 4 and 5).
In order to guarantee a stable and satisfying operating of
the LDO the SIM_VCC output will be connected to a 1.0 mF
bypass ceramic capacitor to the ground. At the input, VBAT
will be bypassed to the ground with a 0.1 mF ceramic
capacitor.
LEVEL SHIFTERS
The level shifters accommodate the voltage difference
that might exist between the microcontroller and the smart
card. The RESET and CLOCK level shifters are
monodirectional and feature both the same architecture.
The bidirectional I/O line provides a way to automatically
adapt the voltage difference between the MCU and the SIM
card in both directions. In addition with the pullup resistor,
an active pullup circuit (Figure 8, Q1 and Q2) provides a fast
charge of the stray capacitance, yielding a rise time fully
within the ISO7816 specifications.
VBAT
Q1
Ilim
R1
SIM_VCC
CIN = 0.1 mF
STOP
+
R2
VREF
COUT = 1.0 mF
MOD_VCC
GND
Figure 8. Simplified Block Diagram of the LDO Voltage Regulator
VDD
SIM_VCC
Q1
18 k
200 ns
Q2
14 k
200 ns
I/O
SIM_I/O
IO/CONTROL
GND
LOGIC
Q3
GND
Figure 9. Basic I/O Line Interface
http://onsemi.com
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