ASM1442 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
ASM1442 Datasheet PDF : 18 Pages
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ASM1442 Data Sheet
Pin Descriptions
This section provides a detailed description of each signal. The following notations are used to describe the signal
type.
I/O Type Definition
I
Input pin
O
Output pin
B
Bi-directional pin
P
Power pin
G
Ground pin
OD
Open Drain
Pin Name
l IN_D[4:1]-
ia IN_D[4:1]+
nt OUT_D[4:1]-
e OUT_D[4:1]+
id HPD
nf HPD_SINK
Co SCL
dia SDA
e SCL_SINK
asm SDA_SINK
Pin No.
47, 44, 41, 38
48, 45, 42, 39
14, 17, 20, 23
13, 16, 19, 22
7
30
9
8
28
29
Type
I
I
O
O
O
I
OD
OD
OD
OD
Descriptions
Negative singal of low-swing TMDS differential input from display
source which output PCI Express electrical signaling with AC
coupling signal.
Positive singal of low-swing TMDS differential input from display
source which output PCI Express electrical signaling with AC
coupling signal
Negative singal of HDMI compliant TMDS differential output to
display sink
Positive singal of HDMI compliant TMDS differential output to
display sink
Low frequency, 0V to 3.3V (nominal) output signal.
Hot plug detection output to display source
Low frequency, 0V to 5V (nominal) input signal. This signal comes
from the HDMI/DVI sink. If the voltage level of HPD_SINK goes high,
it indicates “plugged” state; if the voltage level of HPD_SINK goes
low, it indicates “unplugged”. HPD_SINK is pulled down by an
integrated pull down resistor.
3.3V DDC Clock I/O connecting to display source.
Pulled up by external termination to 3.3V.
Connected to SCL_SINK through voltage-limiting integrated NMOS
passgate internally.
3.3V DDC Data I/O connecting to display source.
Pulled up by external termination to 3.3V.
Connected to SDA_SINK through voltage-limiting integrated
NMOS passgate internally.
5V DDC Clock I/O connecting to sink device.
Pulled up by external termination to 5V.
Connected to SCL through voltage-limiting integrated NMOS
passgate.
5V DDC Data I/O connecting to sink device.
Pulled up by external termination to 5V.
Connected to SDA through voltage-limiting integrated NMOS
passgate.
Enable for level shifter path.
OE#=1: IN_D[4:1]+/- high impedance, OUT_D[4:1]+/- high
OE#
25
I
impedance
OE#=0: IN_D[4:1]+/- is terminated 50Ω internally,
OUT_D[4:1]+/- is Active
Integrate internal pull-down resistor
Enables the bias voltage to the DDC passgate level shifter gates.
DDC_EN
32
I
DDC_EN = 0V: passgate disabled
DDC_EN = 3.3V: passgate enabled
Integrate internal pull-up resistor
REXT
6
I
Connection to 3.4kΩ external resistor.
Strapping Control pins are used to enable Input jitter elimination
EQ_[1:0]
35, 34
I
features. Refer to the table.
Integrate internal pull-up resistor.
5
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