A3V56S30FTP
A3V56S40FTP
256M Single Data Rate Synchronous DRAM
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to
High-Z after the /CAS latency from the burst stop command.
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to
High-Z at the same clock with the burst stop command.
Revision 1.1
Page 19 / 39
Mar., 2010