SC14480 View Datasheet(PDF) - Unspecified
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SC14480 Datasheet PDF : 259 Pages
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weighted capacitors, as depicted in Figure 3. The three
most significant bits are decoded according Table 5.
Each of the seven outputs of the decoder controls a
capacitor (capacitor value is 256 times the value of the
smallest capacitor). At least one of these capacitors
12.0
stays always connected. This gives a guaranteed mini-
mum load for xtal to oscillate. The effect is that
10.0
CLK_FREQ_TRIM_REG value 0x0.XX has the same
varicap value as 0x1.XX (see Figure 4)
8.0
6.0
CLK_FREQ_TRIM_REG
4.0
10 9 8 7 6 ... 1 0
2.0
Decoding
3 --> 7
...
0.0
0
512
1024
1536
trimvalue [dec]
2048
Figure 4 Typical varicap curve
...
256
256 256 256 128 64 ... 2 1
total capacitance = 2048 units
l Figure 3 Frequency trimming
ntia Table 5: CLK_FREQ_TRIM_REG (0xFF400A)
Decoding 3--> 7
e input[2:0]
output[6:0]
fid 2 1 0 6 5 4 3 2 1 0
0 000000001
n 0 0 1 0 0 0 0 0 0 1
0 100000011
o 0 1 1 0 0 0 0 1 1 1
C 1 0 0 0 0 0 1 1 1 1
Trimming might cause phase jumps. In order to reduce
these phase jumps change only one single switch at a
time (this is especially true for the seven largest capac-
itors). Use bit 10...8 for course adjustment and always
increment or decrement this value by 1. Wait approxi-
mately 10 msec to allow the adjustment to settle.
Bits 7...0 are used for fine adjustment.
As an example, the recommended way to change the
frequency trim register from 0x7FF to 0x100 is first to
decrement the value of the three most significant bits
by 1 at a time, and then change the least significant bits
until the desired frequency is reached:
0x7FF --> 0x6FF -->0x5FF --> 0x4FF --> 0x3FF -->
0x2FF --> 0x1FF --> 0x100.
Adjusting the frequency will not affect the PLL behav-
iour. The small phase shifts will be followed by the PLL.
The xtal oscillator is supplied from an internal
LDO_XTAL with output AVD_XTAL and can not be
switched off in the SC14480.
1 010011111
Refer to AN-D-161 “SC14480 Quartz Oscillator” for
1 100111111
more details.
1 111111111
3.4 XTAL DIVIDER SELECTION
The primary XTAL divider must be changed in
CLK_XTAL_CTRL_REG[XTAL_DIV] from ‘1’ (divide by
two) in case of 20.736 MHz xtal or kept to ‘0’ to divide
by one with a 10.368 MHz XTAL.
© 2008-2009 SiTel Semiconductor
17
Version: January 21, 2009 v1.0
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