AEEM View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
AEEM Datasheet PDF : 14 Pages
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Low-Power, Single-/Dual-Level Battery Monitors
with Hysteresis and Integrated µP Reset
VBATT
VCC
MAX6440
LTH
DETECT
RQ
SQ
LBO
HTH
DETECT
LBO TIMEOUT
PERIOD
1.23V
VTH
DETECT
RESET
TIMEOUT
PERIOD
VCC
RESET
VCC
VBATT
VCC
5%
HYST
LTH
DETECT
5%
HYST
HTH
DETECT
1.23V
MAX6441
LBO
TIMEOUT
PERIOD
VTH
DETECT
RESET
TIMEOUT
PERIOD
LBOL
LBOH
LBOLH
RESET
MR
VCC
Figure 1a. Functional Diagram
has stabilized before power-converter or microproces-
sor activity is enabled.
These devices also have an independent µP supervisor
that monitors VCC and provides an active-low reset out-
put. A manual reset function is available to allow the
user to reset the µP with a push-button.
Low-Battery Output
The low-battery outputs are available in active-low
(LBO, LBOL, LBOH, LBOLH), open-drain configura-
tions. The low-battery outputs can be pulled to a volt-
age independent of VCC or VBATT, up to 5.5V. This
allows the device to monitor and operate from direct
battery voltage while interfacing to higher voltage
microprocessors.
The MAX6439/MAX6440 single-output voltage monitors
provide a single low-battery output, LBO. These fixed-
threshold devices assert LBO when VBATT drops below
VLTH and remain asserted for at least 150ms after
VBATT rises above VHTH (see Figure 2). The MAX6441/
MAX6442 triple-output voltage monitors provide three
MR
Figure 1b. Functional Diagram
low-battery outputs: LBOH, LBOL, and LBOLH. LBOH
asserts when VBATT drops below VHTH- and remains
asserted for at least 150ms after VBATT rises above
VHTH+. LBOL asserts when VBATT drops below VLTH-
and remains asserted for at least 150ms after VBATT
rises above VLTH+. LBOLH asserts when VBATT drops
below VLTH- and remains asserted for at least 150ms
after VBATT rises above VHTH+ (see Figure 3). For fast-
rising VBATT input, the LBOL timeout period must com-
plete before the LBOH/LBOLH timeout period begins.
Reset Output
The MAX6439–MAX6442 provide an active-low reset
output (RESET). RESET is asserted when the voltage at
VCC falls below the reset threshold level. Reset remains
asserted for the reset timeout period after VCC exceeds
the threshold. If VCC goes below the reset threshold
before the reset timeout period is completed, the inter-
nal timer restarts. The MAX6439/MAX6441 have open-
drain reset outputs, while the MAX6440/MAX6442 have
push-pull reset outputs (see Figure 4).
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