P3041 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

P3041

P3041 QorIQ Integrated Processor Hardware Specifications

Freescale Semiconductor 

Table of Contents

1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3

1.1 1295 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . .3

1.2 Pinout List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .51

2.2 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3 Power-Down Requirements . . . . . . . . . . . . . . . . . . . . .58

2.4 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.5 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

2.6 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .65

2.7 Power-On Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . .66

2.8 DDR3 and DDR3L SDRAM Controller . . . . . . . . . . . . .66

2.9 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

2.11 Ethernet: Datapath Three-Speed Ethernet (dTSEC),

Management Interface, IEEE Std 1588. . . . . . . . . . . . .78

2.12 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

2.13 Enhanced Local Bus Interface (eLBC) . . . . . . . . . . . . .87

2.14 Enhanced Secure Digital Host Controller (eSDHC) . . .91

2.15 Multicore Programmable Interrupt Controller (MPIC) and

Trust Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

2.16 JTAG Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

2.17 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

2.19 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 100

3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 132

3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3.2 Supply Power Default Setting . . . . . . . . . . . . . . . . . . 139

3.3 Power Supply Design . . . . . . . . . . . . . . . . . . . . . . . . 141

3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 143

3.5 SerDes Block Power Supply Decoupling

Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 143

3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 143

3.7 Recommended Thermal Model . . . . . . . . . . . . . . . . . 152

3.8 Thermal Management Information . . . . . . . . . . . . . . 153

4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

4.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 154

4.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 155

5 Security Fuse Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

6.1 Part Numbering Nomenclature . . . . . . . . . . . . . . . . . 156

6.2 Orderable Part Numbers Addressed by this Document157

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2

2

Freescale Semiconductor

Share Link: