P3041 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

P3041

P3041 QorIQ Integrated Processor Hardware Specifications

Freescale Semiconductor 

This figure shows the major functional units within the chip.

Pin Assignments and Reset States

eOpenPIC

PreBoot

Loader

Security

Monitor

Internal

BootROM

Power Mgmt

SD/MMC

SPI

2x DUART

4x I2C

2x

USB 2.0 PHY

Clocks/Reset

GPIO

CCSR

P3041

128-Kbyte

Backside

L2 Cache

Power Architecture®

e500mc Core

32-Kbyte 32-Kbyte

D-Cache I-Cache

1024-Kbyte

Frontside

CoreNet Platform

Cache

64-bit

DDR3/3L

Memory Controller

PAMU PAMU

PAMU

CoreNet

Coherency Fabric

PAMU

Peripheral

Access Mgmt Unit

PAMU

eLBC

Security

4.2

Queue

Mgr

RapidIO

RMan

Pattern

Match

Engine

2.1

Buffer

Mgr

Frame Manager

Parse, Classify,

Distribute

Buffer

1GE 1GE

10GE

1GE

1GE

1GE

2x DMA

18-Lane 5-GHz SerDes

Real Time Debug

Watchpoint

Cross

Trigger

Perf CoreNet

Monitor Trace

Aurora

Figure 1. Block Diagram

1 Pin Assignments and Reset States

This section contains top view and detailed quadrant views of the FC-PBGA ball map diagram followed by a pinout list.

1.1 1295 FC-PBGA Ball Layout Diagrams

These figures show the FC-PBGA ball map diagrams.

P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

3

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