MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
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COMMANDS
Truth Table 1 provides a quick reference of avail-
able commands. This is followed by a written description
of each command. Two additional Truth Tables appear
16 MEG: x4, x8
SDRAM
following the Operation section; these tables provide
current state/next state information.
TRUTH TABLE 1 – Commands and DQM Operation
(Note: 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column and start READ burst)
WRITE (Select bank and column and
start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CS# RAS# CAS# WE# DQM ADDR DQs NOTES
HXXXX
X
X
L HHHX
X
X
L
L H H X Bank/Row X
3
L H L H X Bank/Col X
4
L H L L X Bank/Col Valid 4
L HH L X
X Active
L L H L X Code
X
5
L L LHX
X
X 6, 7
LL
L
L X Op-code X
2
––––L
–
Active 8
– – – –H
– High-Z 8
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 and BA define the op-code written to the Mode Register.
3. A0-A10 provide row address, and BA determines which bank is made active (BA LOW = Bank 0; BA HIGH = Bank 1).
4. A0-A9 (A9 is a “Don’t Care” for x8) provide column address; A10 HIGH enables the auto precharge feature (nonpersis-
tent), while A10 LOW disables the auto precharge feature; BA determines which bank is being read from or written to
(BA LOW = Bank 0; BA HIGH = Bank 1).
5. For A10 LOW, BA determines which bank is being precharged (BA LOW = Bank 0; BA HIGH = Bank 1); for A10 HIGH,
both banks are precharged and BA is a “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
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