MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC4M8A1TG-10

SYNCHRONOUS DRAM

Micron Technology 

GENERAL DESCRIPTION

The Micron 16Mb SDRAM is a high-speed CMOS,

dynamic random-access memory containing 16,777,216

bits. It is internally configured as a dual memory array

(the 4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual

1 Meg x 8) with a synchronous interface (all signals are

registered on the positive edge of the clock signal, CLK).

Each of the two internal banks is organized with 2,048

rows and either 1,024 columns by 4 bits (4 Meg x 4) or 512

columns by 8 bits (2 Meg x 8).

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an AC-

TIVE command, which is then followed by a READ or

WRITE command. The address bits registered coinci-

dent with the ACTIVE command are used to select the

bank and row to be accessed (BA selects the bank, A0-A10

select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

page, with a burst terminate option. An auto precharge

16 MEG: x4, x8

SDRAM

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst

sequence.

The Micron 16Mb SDRAM uses an internal pipelined

architecture to achieve high-speed operation. This ar-

chitecture is compatible with the 2n rule of prefetch

architectures, but it also allows the column address to be

changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while access-

ing the alternate bank will hide the PRECHARGE cycles

and provide seamless, high-speed, random-access op-

eration.

The Micron 16Mb SDRAM is designed to operate in

3.3V, low-power memory systems. An auto refresh mode

is provided, along with a power-saving, power-down

mode. All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operat-

ing performance, including the ability to synchronously

burst data at a high data rate with automatic column-

address generation, the ability to interleave between in-

ternal banks in order to hide precharge time, and the

capability to randomly change column addresses on each

clock cycle during a burst access.

16 Meg: x4, x8 SDRAM

16MSDRAMx4x8_B.p65 – Rev. 5/98

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1998, Micron Technology, Inc.

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