MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
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16 MEG: x4, x8
SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
32
31
15
14, 13,
12
33
16
18-21, 24-29, 17
4, 8, 37, 41
2, 6, 39, 43
10, 11, 30, 34, 35
5, 9, 36, 40
3, 7, 38, 42
1, 22
23, 44
SYMBOL
CLK
CKE
CS#
RAS#, CAS#,
WE#
DQM
BA
A0-A10
x4: DQ0, 1, 2, 3
x8: DQ1, 3, 4, 6
x4: NC
x8: DQ0, 2, 5, 7
NC
VDDQ
VSSQ
VDD
VSS
TYPE
DESCRIPTION
Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), ACTIVE POWER-DOWN (row active in either bank), or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers, including
CLK, are disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered.
Input
Input/Output Mask: DQM is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQM is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z
state (after a two-clock latency) when DQM is sampled HIGH during a READ
cycle.
Input Bank Address: BA defines to which bank the ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA is also used to program the twelfth
bit of the Mode Register.
Input
Address Inputs: A0-A10 are sampled during the ACTIVE command (row-address
A0-A10) and READ/WRITE command (column-address A0-A9 [x4]; A0-A8 [x8],
with A9 as a “Don’t Care;” and with A10 defining AUTO PRECHARGE) to select
one location out of the memory array in the respective bank. A10 is sampled
during a PRECHARGE command to determine if both banks are to be
precharged (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
Input Data I/O: Data bus.
– No Connect: These pins should be left unconnected.
Input Data I/O: Data bus.
– No Connect: These pins should be left unconnected.
Supply DQ Power.
Supply DQ Ground.
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
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