MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC4M8A1TG-10

SYNCHRONOUS DRAM

Micron Technology 

FUNCTIONAL DESCRIPTION

In general, the SDRAM is a dual memory array (the

4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual

1 Meg x 8) which operates at 3.3V and includes a synchro-

nous interface (all signals are registered on the positive

edge of the clock signal, CLK). Each of the two internal

banks is organized with 2,048 rows and either 1,024 col-

umns by 4 bits (4 Meg x 4) or 512 columns by 8 bits (2 Meg

x 8).

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an AC-

TIVE command, which is then followed by a READ or

WRITE command. The address bits registered coinci-

dent with the ACTIVE command are used to select the

bank and row to be accessed (BA selects the bank, A0-A10

select the row). The address bits (A0-A9; A9 is a “Don’t

Care” for x8) registered coincident with the READ or

WRITE command are used to select the starting column

location for the burst access.

Prior to normal operation, the SDRAM must be ini-

tialized. The following sections provide detailed infor-

mation covering device initialization, register definition,

command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other than

those specified may result in undefined operation. Once

power is applied to VDD and VDDQ (simultaneously) and

the clock is stable, the SDRAM requires a 100µs delay

prior to applying an executable command. The RAS#,

CAS#, WE# and CS# inputs should be held HIGH during

this phase of power-up.

Once the 100µs delay has been satisfied, CKE HIGH

and the PRECHARGE command can be applied (set up

and held with respect to a positive edge of CLK). Both

banks must then be precharged, thereby placing the

device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles are

complete, the SDRAM is ready for Mode Register pro-

gramming. Because the Mode Register will power up in

an unknown state, it should be loaded prior to applying

any operational command.

Register Definition

MODE REGISTER

The Mode Register is used to define the specific mode

of operation of the SDRAM. This definition includes the

selection of a burst length, a burst type, a CAS latency, an

16 MEG: x4, x8

SDRAM

operating mode, and a write burst mode, as shown in

Figure 1. The Mode Register is programmed via the LOAD

MODE REGISTER command and will retain the stored

information until it is programmed again or the device

loses power.

Mode Register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or interleaved),

M4-M6 specify the CAS latency, M7 and M8 specify the

operating mode, M9 specifies the write burst mode, and

M10 and M11 are reserved for future use.

The Mode Register must be loaded when both banks

are idle, and the controller must wait the specified time

before initiating the subsequent operation. Violating ei-

ther of these requirements will result in unspecified op-

eration.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as

shown in Figure 1. The burst length determines the maxi-

mum number of column locations that can be accessed

for a given READ or WRITE command. Burst lengths of 1,

2, 4 or 8 locations are available for both the sequential

and the interleaved burst types, and a full-page burst is

available for the sequential type. The full-page burst is

used in conjunction with the BURST TERMINATE com-

mand to generate arbitrary burst lengths.

Reserved states should not be used, as unknown op-

eration or incompatibility with future versions may re-

sult.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively se-

lected. All accesses for that burst take place within this

block, meaning that the burst will wrap within the block

if a boundary is reached. The block is uniquely selected

by A1-A9 (A9 is “Don’t Care” for x8) when the burst length

is set to two; by A2-A9 (A9 is “Don’t Care” for x8) when the

burst length is set to four; and by A3-A9 (A9 is “Don’t

Care” for x8) when the burst length is set to eight. The

remaining (least significant) address bit(s) is (are) used to

select the starting location within the block. Full-page

bursts wrap within the page if the boundary is reached.

Burst Type

Accesses within a given burst may be programmed to

be either sequential or interleaved; this is referred to as

the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined

by the burst length, the burst type and the starting col-

umn address, as shown in Table 1.

16 Meg: x4, x8 SDRAM

16MSDRAMx4x8_B.p65 – Rev. 5/98

7

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1998, Micron Technology, Inc.

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