MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
| |||
Figure 1
Mode Register Definition
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
11 10 9 8 7 6 5 4 3 2 1 0
Reserved* WB Op Mode CAS Latency BT Burst Length
Mode Register (Mx)
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
M2 M1 M0
000
001
010
011
100
101
110
111
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined Standard Operation
-
-
-
All other states reserved
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
16 MEG: x4, x8
SDRAM
Table 1
Burst Definition
Burst Starting Column Order of Accesses Within a Burst
Length
Address: Type = Sequential Type = Interleaved
A0
2
0
1
A1 A0
00
4
01
10
11
A2 A1 A0
00 0
00 1
01 0
8
01 1
10 0
10 1
11 0
11 1
Full
Page
x4: n = A0-A9
x8: n = A0-A8
(x4:1,024) (location0-1,023)
(x8: 512) (location 0-511)
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2
Cn+3, Cn+4...
…Cn-1,
Cn…
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
NOTE:
1. For a burst length of two, A1-A9 select the block
of two burst (A9 is a “Don’t Care” for x8); A0
selects the starting column within the block.
2. For a burst length of four, A2-A9 select the block
of four burst (A9 is a “Don’t Care” for x8); A0-A1
select the starting column within the block.
3. For a burst length of eight, A3-A9 select the block
of eight burst (A9 is a “Don’t Care” for x8); A0-A2
select the starting column within the block.
4. For a full-page burst, the full row is selected and
A0-A9 select the starting column (A9 is a “Don’t
Care” for x8).
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0-A9 select the unique
column to be accessed (A9 is a “Don’t Care” for
x8), and Mode Register bit M3 is ignored.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
Share Link: 