Audio ICs
!Performing data settings
(1) I2C BUS timing
Parameter
SCL clock frequency
SCL clock hold time, HIGH state
SCL clock hold time, LOW state
SDA and SDL signal start-up time
SDA and SDL signal shut-down time
Set-up time for re-send [start] conditions
Hold time (re-send) [start] conditions
(After hold time ends, initial clock
pulse is generated.)
Set time for [stop] conditions.
Bus free time between [stop] condition
and [start] condition
Data set-up time
BH3856S / BH3856FS
Symbol Min. Typ. Max. Unit
fSCL
0
−
100
kHz
tHIGH
4
−
−
µs
tLOW
4.7
−
−
µs
tr
−
−
1
µs
tf
−
−
0.3
µs
tSU;STA
4.7
−
−
µs
tHD;STA
4
−
−
µs
tSU;STO
4.7
−
−
µs
tBUF
4.7
−
−
µs
tSU;DAT
250
−
−
ns
SLC
SDA start condition
tr
tf
tLOW
tHIGH
tSU ; STA
tHD ; STA
SDA stop condition
tSU ; STO
tBUF
SDA
tSU ; DAT
tHD ; DAT
tSU ; STA = start code set-up time.
tHD ; STA = start code hold time.
tSU ; STO = stop code set-up time.
tBUF = bus free time.
tSU ; DAT = data set-up time.
tHD ; DAT = data hold time.
I2C BUS timing rules