29F040 View Datasheet(PDF) - STMicroelectronics
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29F040 Datasheet PDF : 31 Pages
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M29F040
Table 8. Status Register
DQ
Name
Logic Level
Definition
Note
7
Data
Polling
’1’
Erase Complete
’0’
Erase on Going
DQ
Program Complete
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
DQ
Program on Going
’-1-0-1-0-1-0-1-’ Erase or Program on Going
6
Toggle Bit
’-0-0-0-0-0-0-0-’
Program (’0’ on DQ6)
Complete
’-1-1-1-1-1-1-1-’
Erase or Program
(’1’ on DQ6) Complete
Successive read output complementary
data on DQ6 while Programming or Erase
operations are going on. DQ6 remain at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
5 Error Bit
’1’
Program or Erase Error
This bit is set to ’1’ if P/E.C. has exceded
the specified time limits.
’0’
Program or Erase on Going
’1’
4
’0’
3
Erase
Time Bit
’1’
Erase Timeout Period Expired P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
’0’
Erase Timeout Period on
Going
(ES). An additional block to be erased in
parallel can be entered to the P/E.C.
2
1
0
Note:
Reserved
Reserved
Reserved
Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Data Polling bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid only effective during P/E.C. operation, that is
after the fourth W pulse for programming or after
the sixth W pulse for Erase. It must be performed
at the address being programmed or at an address
within the block being erased. If the byte to be
programmed belongs to a protected block the com-
mand is ignored. If all the blocks selected for era-
sure are protected, DQ7 will set to ’0’ for about
100µs, and then return to previous addressed
memory data. See Figure 9 for the Data Polling
flowchart and Figure 10 for the Data Polling wave-
forms.
Toggle bit (DQ6). When Programming operations
are in progress, successive attempts to read DQ6
will output complementary data. DQ6 will toggle
following toggling of either G or E when G is low.
The operation is completed when two successive
reads yield the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing. The toggle bit is valid only effective during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the byte to be programmed belongs to a
protected block the command will be ignored. If the
blocks selected for erasure are protected, DQ6 will
toggle for about 100µs and then return back to
Read. See Figure 11 for Toggle Bit flowchart and
Figure 12 for Toggle Bit waveforms.
Error bit (DQ5). This bit is set to ’1’ by the P/E.C
when there is a failure of byte programming, block
erase, or chip erase that results in invalid data
being programmed in the memory block. In case of
error in block erase or byte program, the block in
which the error occured or to which the pro-
grammed byte belongs, must be discarded. Other
blocks may still be used. Error bit resets after Reset
(RST) instruction. In case of success, the error bit
will set to ’0’ during Program or Erase and to valid
data after write operation is completed.
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