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HFA3524 View Datasheet(PDF) - Intersil

Part Name
Description
Manufacturer
HFA3524 Datasheet PDF : 15 Pages
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HFA3524
Programmable Divide (N Counter)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care bits.
LSB
MSB
C1 C2 N N N N N N N N N N N N N N N N N N N N
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
(Control bits)
Divide ratio of the programmable divider, N
Program
7-Bit Swallow Counter Divide Ratio (A Counter)
RF
DIVIDE N
N
N
N
N
N
N
RATIO A 7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
NOTES:
12. Divide ratio 0 to 127.
13. B A.
IF
DIVIDE N
N
N
N
N
N
N
RATIO A 7
6
5
4
3
2
1
0
X
X
X
0
0
0
0
1
X
X
X
0
0
0
1
15
X
X
X
1
1
1
1
X = Don’t care condition.
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER
DIVIDE N N N N N N N N N N N
RATIO B 18 17 16 15 14 13 12 11 10 9 8
3
00000000011
4
00000000100
•••••••••••
2047 1 1 1 1 1 1 1 1 1 1 1
NOTES:
14. Divide ratio 3 to 2047 (divide ratios less than 3 are prohibited).
15. B A.
Pulse Swallow Function
fVCO = [(P x B) + A] x fOSC/R
fVCO: Output frequency of external voltage controlled
oscillator (VCO)
B: Preset divide ratio of binary 11-bit programmable
counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter
(0 A 127 {RF}, 0 A 15 {IF}, A B)
fOSC: Output frequency of the external reference frequency
oscillator
R: Preset divide ratio of binary 15-bit programmable
reference counter (3 to 32767)
P: Preset modulus of dual modulus prescaler
(for IF: P = 8 or 16; for RF: P = 32 or 64)
Programmable Modes
Several modes of operation can be programmed with bits
R16-R19 including the phase detector polarity, charge pump
High Z State and the output of the FO/LD pin. The prescaler
and powerdown modes are selected with bits N19 and N20.
The programmable modes are shown in Table 1. Truth table
for the programmable modes and FO/LD output are shown in
Table 2 and Table 3.
TABLE 1. PROGRAMMABLE MODES
C1 C2
R16
R17
R18
R19 R20
0 0 IF Phase
IF ICPO IF DO
Detector Polarity
High Z
IF LD IF FO
0 1 RF Phase
RF ICPO RF DO RF LD RF FO
Detector Polarity
High Z
C1 C2
N19
1 0 IF Prescaler
1 1 RF Prescaler
N20
Powerdown IF
Powerdown RF
10

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