AD7302 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7302 Datasheet PDF : 16 Pages
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AD7302
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1-8 D7–D0
9
CS
10 WR
11 A/B
12 PD
13 LDAC
14 CLR
15 VDD
16 REFIN
17 AGND
18 VOUTB
19 VOUTA
20 DGND
Parallel Data Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of CS
and WR.
Chip Select. Active low logic input.
Write Input. WR is an active low logic input used in conjunction with CS and A/B to write data to the selected
DAC register.
DAC Select. Address pin used to select writing to either DAC A or DAC B.
Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with
the contents of their DAC registers. If LDAC is permanently tied low, the DACs are updated on the rising
edge of WR.
Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all
zeroes and the DAC outputs are cleared to zero volts.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND.
External Reference Input. This can used as the reference for both DACs. The range on this reference input is
1 V to VDD/2. If REFIN is directly tied to VDD the internal VDD/2 reference is selected.
Analog Ground reference point and return point for all analog current on the part.
Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output.
Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output.
Digital Ground reference point and return point for all digital current on the part.
PIN CONFIGURATION
(MSB) DB7 1
20 DGND
DB6 2
DB5 3
19 VOUTA
18 VOUTB
DB4 4
17 AGND
DB3 5 AD7302 16 REFIN
DB2
6
TOP VIEW
(Not to Scale)
15
VDD
DB1 7
14 CLR
(LSB) DB0 8
13 LDAC
CS 9
12 PD
WR 10
11 A/B
REV. 0
–5–
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