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SC88E43 View Datasheet(PDF) - Silan Microelectronics

Part Name
Description
Manufacturer
SC88E43 Datasheet PDF : 25 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Silan
Semiconductors
SC88E43
(continued)
Parameter
Symbol
Conditions
Min Typ Max Unit Notes
Rise time
tR
--
--
200 ns
10
Fall Time
tF
--
--
200 ns
10
DATA to DCLK delay
tDCD DATA, DCLK Pins
6
416
--
11,12,
µs
13
DCLK to DATA delay
tCDD
6
416
--
11,12,
µs
13
Frequency
fDCLK0
1201.6 1202.8 1204 Hz
12
High Time
tCH DCLK Pin
415 416 417
µs
12
Low Time
tCL
415 416 417
µs
12
DCLK to DR delay
tCRD DCLK , DR Pin
415 416 417
µs
12
3-Wire Interface Timming (Mode 1)
Frequency
fDCLK1
--
--
1
MHz
Duty Cycle
DCLK Pin
30
--
70
%
RiseTime
tR1
--
--
20
ns
Rate
Input FSK to DATA delay
tDDS
DCLK , DR Pin
tDDH
500
--
500
--
--
ns
--
ns
a. dBV= decibels above or below a reference voltage of 1Vrms. Signal level is per tone.
b. dBm = decibels above or below a reference power of 1mW into 600 ohms. 0dBm = 0.7746Vrms. Signal
level is per tone.
c. Twist = 20 log (fH amplitude / fL amplitude).
Notes:
1. Both tones have the same amplitude.
2. Band limited random noise 300-3400Hz. Measurement valid only when tone is present.
3. With gain setting as shown in Figure 10. Production tested at VDD =3V±10%, 5V±10%.
4. Range within which tones are accepted.
5. Ranges outside of which tones are rejected.
6. Both mark and space have the same amplitude.
7. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is
300-3400Hz, the Bellcore band is 0-4kHz.
8. Production tested at VDD =5V±10%, 3V±10%.
9. Refer to Figure 16 and 19.
10. into 50pF load.
11. FSK input data at 1200±12 baud.
12. OSCI at 3.579545 MHz±0.1%.
13. Function of signal condition.
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.0 2000.12.31
6

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