33291L View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

33291L

Eight-Output Switch with Serial Peripheral Interface I/O

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

ELECTRICAL PERFORMANCE CURVES

VDD = 5.0 V

SCLK

33291L

Under

Test

SO

CL = 200 pF

CL represents the total capacitance of the test fixture and probe.

Figure 4. Valid Data Delay Time and

Valid Time Test Circuit

VDD = 5.0 V

VPull-Up = 2.5 V

33291L

CS

Under

Test

RL = 1.0 kΩ

SO

CL = 20 pF

CL represents the total capacitance of the test fixture and probe.

Figure 5. Enable and Disable Time Test Circuit

SCLK

tR(SI)

< 50 ns

0.7 VDD

50%

tDLY(LH)

SO

(Low-to-High)

SO

(High-to-Low)

0.2 VDD

tVALID

0.7 VDD

tR(SO)

tF(SO)

tDLY(HL)

tF(SI)

< 50 ns

5.0 V

0.7 VDD

0.2 VDD 0

VOH

VOL

0.2 VDD

VOH

VOL

SO (Low-to-High) is for an output with internal conditions such that

the low-to-high transition of CS causes the SO output to switch from

high to low.

Figure 6. Valid Data Delay Time and

Valid Time Waveforms

tR(SI)

CS

0.2 VDD

< 50 ns

90%

10%

tF(SI)

< 50 ns

0.7 VDD

5.0 V

0

SO

(High-to-Low)

SO

(Low-to-High)

tSO(EN)

90%

tSO(EN)

10%

tSO(DIS)

VTri-State

10%

tSO(DIS)

90%

tSO(dis

VOH

VTri-State

1. SO (high-to-low) waveform is for SO output with internal conditions such

that SO output is low except when an output is disabled as a result of de-

tecting a circuit fault with CS in a High Logic state; e.g., open load.

2. SO (low-to-high) waveform is for SO output with internal conditions such

that SO output is high except when an output is disabled as a result of de-

tecting a circuit fault with CS in a High Logic state; e.g., shortened load.

Figure 7. Enable and Disable Time Waveforms

Analog Integrated Circuit Device Data

Freescale Semiconductor

33291L

9

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