General Product Characteristics
Table 9. Pin Logic Thresholds
Pin Name
Internal
Termination (17)
Parameter
MISO, INT
CMOS
Output Low
Output High
Load Condition
Min
-100 A
0.0
100 A
SPIVCC - 0.2
Max (20)
0.2
SPIVCC
Unit
V
V
PUMS1,2,3,4,5
Input Low
-
PUMSxS = 0
Input High
-
PUMSxS = 1
0.0
0.3
V
1.0
VCOREDIG
V
ICTEST
Input Low
Input High
-
0.0
0.3
V
-
1.1
1.7
V
Input Low
-
0.0
0.3
V
SW1CFG, SW4CFG
Input Mid
-
1.3
2.0
V
Input High
-
2.5
3.1
V
Notes
13. SPIVCC is typically connected to the output of buck regulator SW5 and set to 1.800 V
14. Input has internal pull-up to VCOREDIG equivalent to 200 kOhm
15. Input state is latched in first phase of cold start, refer to Serial Interfaces for a description of the PUMS configuration
16. Input state is not latched
17. A weak pull-down represents a nominal internal pull-down of 100 nA unless otherwise noted
18. RESETB, RESETBMCU, SDWNB, SW1PWGD, SW2PWGD have open drain outputs, external pull-ups are required
19. SPIVCC needs to remain enabled for proper detection of WDI High to avoid involuntary shutdown
20. The maximum should never exceed the maximum rating of the pin as given in Pin Connections
21. The weak pull-down on CS is disabled if a VIH is detected at startup to avoid extra consumption in I2C mode
22. The output drive strength is programmable
Notes
MISO
(13) (22)
MISO
(13) (22)
(15)
(15)
(16)
(16)
Analog Integrated Circuit Device Data
Freescale Semiconductor
MC34708
18