34709 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

34709

Power Management Integrated Circuit (PMIC) for i.MX50/53 Families

Freescale Semiconductor 

Functional Block Description

Table 9. Power-up Defaults

i.MX

Reserved

53

LPM

53

53

53

53

DDR2 DDR3 LVDDR3 LVDDR2

50

50

50

50

50

50

VUSB(29)

Reserved

3.3

3.3

3.3

3.3

3.3

3.3

3.3

3.3

3.3

3.3

3.3

VUSB2

Reserved

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

VSRTC

Reserved

1.2

1.3

1.3

1.3

1.3

1.2

1.2

1.2

1.2

1.2

1.2

VPLL

Reserved

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.8

1.8

VREFDDR Reserved

On

On

On

On

On

On

On

On

On

On

On

VDAC

Reserved

2.775

2.775

2.775

2.775

2.775

2.5

2.5

2.5

2.5

2.5

2.5

VGEN1

Reserved

1.2

1.3

1.3

1.3

1.3

1.2

1.2

1.2

1.2

1.2

1.2

VGEN2

Reserved

2.5

2.5

2.5

2.5

2.5

3.1

3.1

3.1

3.1

2.5

2.5

Notes

28. The SWx node are activated in APS mode when enabled by the start-up sequencer.

29. VUSB is supplied by SWBST.

The power-up sequence is shown in Tables 10 and 11. VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer

start-up.

Table 10. Power-up Sequence i.MX53

Tap x 2.0 ms

PUMS [4:1] = [0101,0110,0111,1000,1001] (i.MX53)

0

SW2 (VCC)

1

VPLL (NVCC_CKIH = 1.8 V)

2

VGEN2 (VDD_REG= 2.5 V, external PNP

3

SW3 (VDDA)

4

SW1A/B (VDDGP)

5

SW4A/B, VREFDDR (DDR/SYS)

6

7

SW5 (I/O), VGEN1

8

VUSB, VUSB2

9

VDAC

34709

21

Table 11. Power-up Sequence i.MX50

Tap x 2.0 ms PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.MX50/I.MX53)

0

SW2

1

SW3

2

SW1A/B

3

VDAC

4

SW4A/B, VREFDDR

5

SW5

6

VGEN2, VUSB2

7

VPLL

8

VGEN1

9

VUSB

Analog Integrated Circuit Device Data

Freescale Semiconductor

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