5102ALP Datasheet PDF - MAXWELL TECHNOLOGIES

5102ALP View Datasheet(PDF) - MAXWELL TECHNOLOGIES

Part Name

Description

Manufacturer

5102ALP

16-Bit, 20 KHz A/D Converter

MAXWELL TECHNOLOGIES

5102ALP Datasheet PDF : 14 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

16-Bit, 20 KHz A/D Converter

5102ALP

TABLE 3. ANALOG CHARACTERISTICS

(TA = TMIN TO TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; FULL-SCALE INPUT SINEWAVE, 200 HZ; CLKIN = 1.6 MHZ; fS = 20 KHZ;

BIPOLAR MODE;

FRN MODE; AIN1 AND AIN2 TIED TOGETHER, EACH CHANNEL TESTED SEPARATELY; ANALOG SOURCE IMPEDANCE = 50 W WITH 1000 PF TO AGND

UNLESS OTHERWISE SPECIFIED)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Power Supply Current 11

Positive Analog

Negative Analog

(SLEEP High) Positive Digital

Negative Digital

Power Consumption 11, 12

(SLEEP High)

(SLEEP Low)

Power Supply Rejection 13

Positive Supplies

Negative Supplies

IA+

8.5

IA-

-7.7

-11

ID+

0.5

1.5

ID-

-0.5

-1.5

Pdo

130

Pds

PSR

1. Minimum resolution for which no missing codes are guaranteed over the specified temperature range.

2. Applies after calibration at any temperature within the specified temperature range.

3. Total drift over specified temperature range after calibration at power-up at 25°C.

4. Guaranteed by characterization (5102A die).

5. Wideband noise aliased into the baseband. Referred to the input.

6. Applied only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.

7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN

mode). In PDT, RBT, and SSC modes, asynchronrous delay between the falling edge of HOLD and the start of conversion may

add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns.

8. The 5102ALPRP requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µ s of fine charge. FRN mode

allows 9 clock cycles for fine charge which provides for the minimum 5.625 µ s with a 1.6 MHz clock; however, in PDT, RBT, or

SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles.

9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition

and conversion times described above.

10.Typical value (measured).

11. All outputs unloaded. All inputs at VD+ or DGND.

12.Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).

13.With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipo-

lar mode to 90 dB.

TABLE 4. 5102ALP SWITCHING CHARACTERISTICS

(TA = TMIN TO TMAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; INPUTS: LOGIC 0 = 0V, LOGIC 1 = VD+; CL = 50 PF)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

CLKIN Period 1, 2

CLKIN Low Time

CLKIN High Time

tclk

0.5

tclkl

200

tclkh

200

µs

01.17.05 REV 3 All data sheets are subject to change without notice 4

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