DSP56F801PB View Datasheet(PDF) - Motorola => Freescale
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Description
Manufacturer
DSP56F801PB Datasheet PDF : 44 Pages
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Freescale Semiconductor, Inc.
Table 6. PLL and Clock (Continued)
No. of Signal
Pins Name
Signal
State
Type During Reset
Signal Description
1
XTAL Output
Chip-
Crystal Oscillator Output—This output should be connected to an
driven 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
GPIOB3 Input/
Output
Input
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.5.3.
Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO)
pin that can be programmed as an input or output pin. This I/O can be
utilized when using the on-chip relaxation oscillator so the XTAL pin is
not needed.
2.4 Interrupt and Program Control Signals
Table 7. Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State
During
Reset
Signal Description
1
IRQA
Input
Input
External Interrupt Request A—The IRQA input is a
(Schmitt)
synchronized external interrupt request that indicates that an
external device is requesting service. It can be programmed to be
level-sensitive or negative-edge- triggered.
1
RESET
Input
Input
Reset—This input is a direct hardware reset on the processor.
(Schmitt)
When RESET is asserted low, the hybrid controller is initialized
and placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial
chip operating mode is latched from the EXTBOOT pin. The
internal reset signal will be deasserted synchronous with the
internal clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET, but do not assert TRST.
2.5 Pulse Width Modulator (PWM) Signals
Table 8. Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
PWMA0-5 Output
Tri-stated PWMA0-5— These are six PWMA output pins.
1
FAULTA0
Input
(Schmitt)
Input
FAULTA0— This fault input pin is used for disabling selected
PWMA outputs in cases where fault conditions originate off-
chip.
8
56F801 Technical Data
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