56F803 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
56F803 Datasheet PDF : 48 Pages
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Freescale Semiconductor, Inc.
Table 9. Bus Control Signals
No. of Signal Signal State During
Pins Name Type
Reset
Signal Description
1
PS Output Tri-stated Program Memory Select—PS is asserted low for external Program
memory access.
1
DS Output Tri-stated Data Memory Select—DS is asserted low for external Data memory
access.
1
WR Output Tri-stated Write Enable—WR is asserted during external memory write cycles.
When WR is asserted low, pins D0–D15 become outputs and the
device puts data on the bus. When WR is deasserted high, the
external data is latched inside the external device. When WR is
asserted, it qualifies the A0–A15, PS, and DS pins. WR can be
connected directly to the WE pin of a Static RAM.
1
RD Output Tri-stated Read Enable—RD is asserted during external memory read cycles.
When RD is asserted low, pins D0–D15 become inputs and an
external device is enabled onto the device data bus. When RD is
deasserted high, the external data is latched inside the hybrid
controller. When RD is asserted, it qualifies the A0–A15, PS, and DS
pins. RD can be connected directly to the OE pin of a Static RAM or
ROM.
2.5 Interrupt and Program Control Signals
Table 10. Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
IRQA
Input
Input
External Interrupt Request A—The IRQA input is a
(Schmitt)
synchronized external interrupt request indicating an
external device is requesting service. It can be programmed
to be level-sensitive or negative-edge- triggered.
1
IRQB
Input
Input
External Interrupt Request B—The IRQB input is an
(Schmitt)
external interrupt request indicating an external device is
requesting service. It can be programmed to be level-
sensitive or negative-edge-triggered.
10
56F803 Technical Data
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