56F803 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
56F803 Datasheet PDF : 48 Pages
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Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM) Signals
Table 10. Interrupt and Program Control Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
RESET
Input
(Schmitt)
1
EXTBOOT
Input
(Schmitt)
Input
Input
Reset—This input is a direct hardware reset on the
processor. When RESET is asserted low, the hybrid
controller is initialized and placed in the Reset state. A
Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is
latched from the EXTBOOT pin. The internal reset signal will
be deasserted synchronous with the internal clocks, after a
fixed number of internal clocks.
To ensure a complete hardware reset, RESET and TRST
should be asserted together. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
External Boot—This input is tied to VDD to force device to
boot from off-chip memory. Otherwise, it is tied to VSS.
2.6 Pulse Width Modulator (PWM) Signals
Table 11. Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal State During
Type
Reset
Signal Description
6
PWMA0–5 Output
Tri-stated PWMA0–5— These are six PWMA output pins.
3
ISA0–2
Input
Input
ISA0–2— These three input current status pins are used for
(Schmitt)
top/bottom pulse width correction in complementary channel
operation for PWMA.
3 FAULTA0–2 Input
(Schmitt)
Input
FAULTA0–2— These three fault input pins are used for
disabling selected PWMA outputs in cases where fault
conditions originate off-chip.
56F803 Technical Data
11
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