Freescale Semiconductor, Inc.
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2 and
as illustrated in Figure 2. In Table 3 through Table 18, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group
Number of
Pins
Detailed
Description
Power (VDD or VDDA)
Ground (VSS or VSSA)
Supply Capacitors
PLL and Clock
Address Bus1
Data Bus
Bus Control
Interrupt and Program Control
Pulse Width Modulator (PWM) Port
Serial Peripheral Interface (SPI) Port1
Quadrature Decoder Port2
Serial Communications Interface (SCI) Port1
CAN Port
Analog to Digital Converter (ADC) Port
Quad Timer Module Port
JTAG/On-Chip Emulation (OnCE)
1. Alternately, GPIO pins
2. Alternately, Quad Timer pins
7
Table 3
7
Table 4
2
Table 5
3
Table 6
16
Table 7
16
Table 8
4
Table 9
4
Table 10
12
Table 11
4
Table 12
4
Table 13
2
Table 14
2
Table 15
9
Table 16
2
Table 17
6
Table 18
6
56F803 Technical Data
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