DSP56F805/D View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56F805/D Datasheet PDF : 48 Pages
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Freescale Semiconductor, Inc.
GPIO Signals
Table 10. Interrupt and Program Control Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State
During
Reset
Signal Description
1
RSTO
Output Output Reset Output—This output reflects the internal reset state of the
chip.
1
EXTBOOT
Input
Input External Boot—This input is tied to VDD to force device to boot
(Schmitt)
from off-chip memory. Otherwise, it is tied to VSS.
2.6 GPIO Signals
Table 11. Dedicated General Purpose Input/Output (GPIO) Signals
No. of
Pins
Signal
Name
Signal State During
Type
Reset
Signal Description
8 GPIOB0– Input
GPIOB7
or
Output
6 GPIOD0– Input
GPIOD5
or
Output
Input
Input
Port B GPIO—These eight dedicated General Purpose I/O
(GPIO) pins can be individually programmed as input or output
pins.
After reset, the default state is GPIO input.
Port D GPIO—These six dedicated General Purpose I/O (GPIO)
pins can be individually programmed as input or output pins.
After reset, the default state is GPIO input.
2.7 Pulse Width Modulator (PWM) Signals
Table 12. Pulse Width Modulator (PWMA and PWMB) Signals
No. of
Pins
Signal Name
Signal
Type
State During
Reset
Signal Description
6
PWMA0–5
Output
Tri- stated PWMA0–5—These are six PWMA output pins.
3
ISA0–2
Input
Input
ISA0–2—These three input current status pins are used for
(Schmitt)
top/bottom pulse width correction in complementary
channel operation for PWMA.
4
FAULTA0–3
Input
(Schmitt)
Input
FAULTA0–3—These four Fault input pins are used for
disabling selected PWMA outputs in cases where fault
conditions originate off-chip.
6
PWMB0–5 Output
Output
PWMB0–5—These are six PWMB output pins.
3
ISB0–2
Input
Input
ISB0–2— These three input current status pins are used
(Schmitt)
for top/bottom pulse width correction in complementary
channel operation for PWMB.
4
FAULTB0–3
Input
(Schmitt)
Input
FAULTB0–3—These four Fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.
56F805 Technical Data
11
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