Freescale Semiconductor, Inc.
10.12 Quad Timer Timing
Quad Timer Timing
Table 10-19 Timer Timing1, 2
Characteristic
Symbol
Min
Max
Timer input period
PIN
2T + 6
—
Timer input high / low period
PINHL
1T + 3
—
Timer output period
POUT
1T - 3
—
Timer output high / low period
POUTHL
0.5T - 3
—
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
Unit
See Figure
ns
10-14
ns
10-14
ns
10-14
ns
10-14
Timer Inputs
PIN
PINHL
PINHL
Timer Outputs
POUT
POUTHL
POUTHL
Figure 10-14 Timer Timing
10.13 Quadrature Decoder Timing
Table 10-20 Quadrature Decoder Timing1, 2
Characteristic
Symbol
Min
Max
Quadrature input period
PIN
4T + 12
—
Quadrature input high / low period
PHL
2T + 6
—
Quadrature phase period
PPH
1T + 3
—
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns.
2. Parameters listed are guaranteed by design.
Unit
ns
ns
ns
See Figure
10-15
10-15
10-15
56F8357 Technical Data
141
Preliminary
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