56F8357 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
56F8357 Datasheet PDF : 160 Pages
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Freescale Semiconductor, Inc.
MC56F8357/D
Rev. 7.0, 06/2004
56F8357
Preliminary Technical Data
56F8357 16-bit Digital Signal Processor
• Up to 60 MIPS at 60MHz core frequency
• Temperature Sensor
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 4MB of off-chip program and 32MB
of data memory
• Chip Select Logic for glueless interface to ROM
and SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB Boot Flash
• Two 6-channel PWM modules
• Two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 76 GPIO lines
• 160-pin LQFP Package
• Four 4-channel, 12-bit ADCs
RSTO EMI_MODE
RESET EXTBOOT
OCR_DIS
VPP VCAP VDD
VSS
VDDA VSSA
5
2
4
7
6
2
* Configuration
shown for on-chip
2.5V regulator
6 PWM Outputs
PWMA
3
Current Sense Inputs or GPIOC
4
Fault Inputs
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
6 PWM Outputs
PWMB
3
Current Sense Inputs or GPIOD
4
Fault Inputs
4
AD0
4
ADCA
AD1
Program Controller
and
Hardware Looping Unit
PAB
PDB
CDBR
CDBW
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
5
VREF
Memory
4
AD0 ADCB Program Memory
4
AD1
128K x 16 Flash
2K x 16 RAM
TEMP_SENSE
Boot ROM
Quadrature
8K x 16 Flash
4
Decoder 0 or
Quad
Data Memory
4K x 16 Flash
Timer or /
8K x 16 RAM
GPIOC
Quadrature
Decoder 1 or
4
Quad
Timer B or
SPI1 or GPIOC
2
Quad
Timer C or
Decoding
GPIOE Peripherals
Quad
4
Timer D or
GPIOE
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
IPAB
Control
IPWDB IPRDB
Clock
resets
6
2
External
Address Bus 8
Switch
4
1
3
External Data 7
Bus Switch 8
Bus Control 6
PLL
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
**See Table 2-2
for explanation
2
FlexCAN
SPI0 or SCI1 or SCI0 or COP/
GPIOE GPIOD GPIOE Watchdog
Interrupt
Controller
System P
Integration
O
R
Module
Clock O
Generator
S
C
XTAL
EXTAL
4
2
2
IRQA IRQB
CLKO CLKMODE
56F8357 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
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