56F8357 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

56F8357

16-bit Hybrid Controllers

Unspecified 

Introduction

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8357 and 56F8157 are organized into functional groups, as detailed

in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals

present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins in Package

56F8357

56F8157

Power (VDD or VDDA)

9

9

Power Option Control

1

1

Ground (VSS or VSSA)

7

7

Supply Capacitors1 & VPP

6

6

PLL and Clock

4

4

Address Bus

24

24

Data Bus

16

16

Bus Control

10

10

Interrupt and Program Control

6

6

Pulse Width Modulator (PWM) Ports

26

13

Serial Peripheral Interface (SPI) Port 0

4

4

Serial Peripheral Interface (SPI) Port 1

—

4

Quadrature Decoder Port 02

4

4

Quadrature Decoder Port 13

4

—

Serial Communications Interface (SCI) Ports2

4

4

CAN Ports

2

—

Analog to Digital Converter (ADC) Ports

21

21

Timer Module Ports

6

2

JTAG/Enhanced On-Chip Emulation (EOnCE)

5

5

Temperature Sense

1

—

Dedicated GPIO

—

7

1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs

2. Alternately, can function as Quad Timer pins

3. Pins in this section can function as Quad Timer, SPI #1, or GPIO

56F8357 Technical Data, Rev. 8.0

Freescale Semiconductor

15

Preliminary

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