56F802X View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

56F802X

16-bit Digital Signal Controllers

Freescale Semiconductor 

56F8025 Signal Pins

2.2 56F8025 Signal Pins

After reset, each pin is configured for its primary function (listed first). Any alternate functionality must

be programmed.

Table 2-3 56F8025 Signal and Package Information for the 44-Pin LQFP

Signal LQFP

Name Pin No.

Type

State During

Reset

Signal Description

VDD

VDD

VSS

VSS

VSS

VDDA

VSSA

VCAP

VCAP

RESET

(GPIOA7)

29

Supply

Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface.

35

17

Supply

28

Supply VSS — These pins provide ground for chip logic and I/O drivers.

36

11

Supply

12

Supply

18

Supply

34

Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It

must be connected to a clean analog power supply.

Supply ADC Analog Ground — This pin supplies an analog ground to the

ADC modules.

Supply

VCAP — Connect this pin to a 4.7μF or greater bypass capacitor in

order to bypass the core voltage regulator, required for proper chip

operation. See Section 10.2.1.

21

Input

Input, Reset — This input is a direct hardware reset on the processor.

internal When RESET is asserted low, the chip is initialized and placed in the

pull-up reset state. A Schmitt trigger input is used for noise immunity. The

enabled internal reset signal will be deasserted synchronous with the internal

clocks after a fixed number of internal clocks.

Input/Open

Drain

Output

Port A GPIO — This GPIO pin can be individually programmed as

an input or open drain output pin. Note that RESET functionality is

disabled in this mode and the chip can only be reset via POR, COP

reset, or software reset.

After reset, the default state is RESET.

Return to Table 2-2

56F8025 Data Sheet, Rev. 3

Freescale Semiconductor

21

Preliminary

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