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56F802X View Datasheet(PDF) - Freescale Semiconductor

Part Name
Description
Manufacturer
56F802X
Freescale
Freescale Semiconductor Freescale
56F802X Datasheet PDF : 160 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
56F8025 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB (16K x 16) Program Flash
• 4KB (2K x 16) Unified Data/Program RAM
• One 6-channel PWM module
• Two 4-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two Internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I2C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 35 GPIO lines
• 44-pin LQFP Package
RESET or
GPIOA
4
VCAP VDD
2
2
VSS
3
VDDA VSSA
11
PWM
or TMRA or CMP
or GPIOA
JTAG/EOnCE
Port or
GPIOD
Digital Reg Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
DAC
4 AD0
ADC
or CMP
or GPIOC
4 AD1
Memory
Program Memory
16K x 16 Flash
Unified Data /
Program RAM
2K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I2C
or CMP
or GPIOB
QSPI
or PWM
or I2C
or TMRA
or GPIOB
QSCI
or PWM
or I2C
or TMRA
or GPIOB
2
4
3
COP/
Watchdog
Interrupt
Controller
System P
Integration
O
R
Module
Clock
Generator*
O
S
C
*Includes On-Chip
Relaxation Oscillator
56F8025 Block Diagram
Freescale Semiconductor
Preliminary
56F8025 Data Sheet, Rev. 3
XTAL, CLKIN, or
GPIOD
EXTAL or GPIOD
3

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