56F802X View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

56F802X

16-bit Digital Signal Controllers

Freescale Semiconductor 

56F8025 Description

• Two analog Comparators (CMPs)

— Selectable input source includes external pins, DACs

— Programmable output polarity

— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs

— Output falling and rising edge detection able to generate interrupts

• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources

• Up to 35 General-Purpose I/O (GPIO) pins with 5V tolerance

• Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module

• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals

• Clock sources:

— On-chip relaxation oscillator

— External clock: Crystal oscillator, ceramic resonator, and external clock source

• JTAG/EOnCE debug programming interface for real-time debugging

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V tolerance

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

• ADC smart power management

• Each peripheral can be individually disabled to save power

1.2 56F8025 Description

The 56F8025 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It

combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with

a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8025 is well-suited for many applications.

The 56F8025 includes many peripherals that are especially useful for industrial control, motion control,

home appliances, general-purpose inverters, smart sensors, fire and security systems, switched-mode

power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8025 supports program execution from internal memories. Two data operands can be accessed

from the on-chip data RAM per instruction cycle. The 56F8025 also offers up to 35 General-Purpose

Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8025 Digital Signal Controller includes 32KB of Program Flash and 4KB of Unified

56F8025 Data Sheet, Rev. 3

Freescale Semiconductor

7

Preliminary

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