DSP56800ERM(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56800ERM
(Rev.:2006)

Digital Signal Controller

Freescale Semiconductor 

Recommended Operating Conditions

— Output falling and rising edge detection able to generate interrupts

• Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources

• Up to 35 General-Purpose I/O (GPIO) pins with 5V tolerance

• Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module

• Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals

• Clock sources:

— On-chip relaxation oscillator

— External clock: Crystal oscillator, ceramic resonator, and external clock source

• JTAG/EOnCE debug programming interface for real-time debugging

5 Recommended Operating Conditions

Table 1. Recommended Operating Conditions

(VREFL x= 0V, VSSA = 0V, VSS = 0V)

Characteristic

Symbol

Notes

Min

Typ

Max

Unit

Supply voltage

ADC Reference Voltage High

Voltage difference VDD_IO to VDDA

Voltage difference VSS_IO to VSSA

Device Clock Frequency

Using relaxation oscillator

Using external clock source

Input Voltage High (digital inputs)

Input Voltage Low (digital inputs)

Oscillator Input Voltage High

XTAL not driven by an external clock

XTAL driven by an external clock source

Oscillator Input Voltage Low

Analog Input Voltage

VDD,

VDDA

3

3.3

3.6

V

VREFHx

3.0

VDDA

V

ΔVDD

-0.1

0

0.1

V

ΔVSS

-0.3

0

0.3

V

FSYSCLK

1

32

MHz

0

32

VIH

Pin Groups 1, 2

2.0

5.5

V

VIL

Pin Groups 1, 2

-0.3

0.8

V

VIHOSC

Pin Group 4

VDDA - 0.8

2.0

VDDA + 0.3

V

VDDA + 0.3

VILOSC

Pin Group 4

-0.3

0.8

V

VIA

Pin Group 3

0.0

VDDA

V

56F8025 Digital Signal Controller Product Brief, Rev. 0

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

5

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