DSP56800ERM(2006) View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56800ERM Datasheet PDF : 12 Pages
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56F8025 Description
The 56F8025 supports program execution from internal memories. Two data operands can be accessed
from the on-chip data RAM per instruction cycle. The 56F8025 also offers up to 35 General-Purpose
Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F8025 Digital Signal Controller includes 32KB of Program Flash and 4KB of Unified
Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.
Program Flash page erase size is 512 Bytes (256 Words).
A full set of programmable peripherals — PWM, ADCs, QSCI, QSPI, I2C, PIT, Quad Timers, DACs, and
analog comparators — supports various applications. Each peripheral can be independently shut down to
save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).
RESET or
GPIOA
4
VCAP
2
VDD
2
VSS_IO VDDA
3
VSSA
11
PWM
or TMRA or CMP
or GPIOA
JTAG/EOnCE
Port or
GPIOD
Digital Reg Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
DAC
4 AD0
ADC
or CMP
or GPIOC
4 AD1
Memory
Program Memory
16K x 16 Flash
Unified Data /
Program RAM
2K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I2C
or CMP
or GPIOB
2
QSPI
or PWM
or I2C
or TMRA
or GPIOB
4
QSCI
or PWM
or I2C
or TMRA
or GPIOB
3
COP/
Watchdog
Interrupt
Controller
System P
Integration
O
R
Module
Clock
Generator*
O
S
C
*Includes On-Chip
Relaxation Oscillator
Figure 1. 56F8025 Block Diagram
XTAL, CLKIN, or
GPIOD
EXTAL or GPIOD
56F8025 Digital Signal Controller Product Brief, Rev. 0
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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