56F8355(2004) View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
56F8355 Datasheet PDF : 164 Pages
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Device Description
• 49 General Purpose I/O (GPIO) pins; 28 pins dedicated to GPIO
• External reset input pin for hardware reset
• External reset output pin for system reset
• Integrated low-voltage interrupt module
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
• Software-programmable, Phase Lock Loop-based frequency synthesizer for the core clock
1.1.5 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8355 and 56F8155 are members of the 56800E core-based family of hybrid controllers. It
combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality
of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution.
Because of its low cost, configuration flexibility, and compact program code, the 56F8355 and 56F8155
are well-suited for many applications. The devices include many peripherals that are especially useful for
motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and
control, automotive control (56F8355 only), engine management, noise suppression, remote utility
metering, industrial control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F8355 and 56F8155 support program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. These devices also provide two external
dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
1.2.1 56F8355 Features
The 56F8355 hybrid controller includes 256KB of Program Flash and 8KB of Data Flash (each
programmable through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. A total of
16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
56F8355 Technical Data, Rev. 5.0
Freescale Semiconductor
7
Preliminary
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