56F8355 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
56F8355 Datasheet PDF : 172 Pages
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Table of Contents
Part 1 Overview . . . . . . . . . . . . . . . . . . . . . 6
1.1 56F8355/56F8155 Features . . . . . . . . . . . 6
1.2 Device Description . . . . . . . . . . . . . . . . . . 8
1.3 Award-Winning Development
Environment . . . . . . . . . . . . . . . . . . 10
1.4 Architecture Block Diagram . . . . . . . . . . 10
1.5 Product Documentation . . . . . . . . . . . . . 14
1.6 Data Sheet Conventions. . . . . . . . . . . . . 15
Part 2 Signal/Connection Descriptions. 16
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Signal Pins . . . . . . . . . . . . . . . . . . . . . . . 19
Part 3 On-Chip Clock Synthesis (OCCS) 35
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 External Clock Operation . . . . . . . . . . . . 35
3.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . 37
Part 4 Memory Map . . . . . . . . . . . . . . . . . 37
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 37
4.2 Program Map . . . . . . . . . . . . . . . . . . . . . 38
4.3 Interrupt Vector Table . . . . . . . . . . . . . . . 40
4.4 Data Map . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5 Flash Memory Map . . . . . . . . . . . . . . . . . 43
4.6 EOnCE Memory Map . . . . . . . . . . . . . . . 44
4.7 Peripheral Memory Mapped Registers . . 45
4.8 Factory Programmed Memory . . . . . . . . 72
Part 5 Interrupt Controller (ITCN) . . . . . 72
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 72
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3 Functional Description . . . . . . . . . . . . . . 73
5.4 Block Diagram . . . . . . . . . . . . . . . . . . . . 75
5.5 Operating Modes . . . . . . . . . . . . . . . . . . 75
5.6 Register Descriptions . . . . . . . . . . . . . . . 76
5.7 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 102
Part 6 System Integration Module (SIM)104
6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 104
6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3 Operating Modes . . . . . . . . . . . . . . . . . 104
6.4 Operating Mode Register . . . . . . . . . . . 105
6.5 Register Descriptions . . . . . . . . . . . . . . 106
6.6 Clock Generation Overview . . . . . . . . . 120
6.7 Power Down Modes Overview . . . . . . . 120
6.8 Stop and Wait Mode Disable Function . 121
6.9 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 122
Part 7 Security Features. . . . . . . . . . . . 122
7.1 Operation with Security Enabled . . . . . 122
7.2 Flash Access Blocking Mechanisms. . . 123
Part 8 General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . 125
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 125
8.2 Memory Maps . . . . . . . . . . . . . . . . . . . . 126
8.3 Configuration . . . . . . . . . . . . . . . . . . . . 126
Part 9 Joint Test Action Group (JTAG) 131
9.1 56F8355 Information. . . . . . . . . . . . . . . 131
Part 10Specifications . . . . . . . . . . . . . . . 131
10.1 General Characteristics . . . . . . . . . . . . 131
10.2 DC Electrical Characteristics . . . . . . . . 135
10.3 AC Electrical Characteristics . . . . . . . . 139
10.4 Flash Memory Characteristics . . . . . . . 140
10.5 External Clock Operation Timing . . . . . 140
10.6 Phase Locked Loop Timing . . . . . . . . . 141
10.7 Crystal Oscillator Timing . . . . . . . . . . . . 141
10.8 Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 142
10.9 Serial Peripheral Interface (SPI)
Timing . . . . . . . . . . . . . . . . . . . . . 144
10.10 Quad Timer Timing . . . . . . . . . . . . . . . . 147
10.11 Quadrature Decoder Timing . . . . . . . . . 148
10.12 Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . 149
10.13 Controller Area Network (CAN) Timing. 149
10.14 JTAG Timing. . . . . . . . . . . . . . . . . . . . . 150
10.15 Analog-to-Digital Converter (ADC)
Parameters. . . . . . . . . . . . . . . . . . 151
10.16 Equivalent Circuit for ADC Inputs . . . . . 155
10.17 Power Consumption . . . . . . . . . . . . . . . 155
Part 11Packaging . . . . . . . . . . . . . . . . . . 157
11.1 56F8355 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 157
11.2 56F8155 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 160
Part 12Design Considerations . . . . . . . 165
12.1 Thermal Design Considerations . . . . . . 165
12.2 Electrical Design Considerations . . . . . 166
12.3 Power Distribution and I/O Ring
Implementation167
Part 13Ordering Information . . . . . . . . . 168
56F8355 Technical Data, Rev. 17
Freescale Semiconductor
5
Preliminary
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